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MC74VHC595 8- Bit Shift Register with Output Storage Register
(3- State) The MC74VHC595 is an advanced high speed 8- shift register -bit with an output storage register fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC595 contains an 8-bit static shift register which feeds an 8- storage register. -bit Shift operation is accomplished on the positive going transition of the Shift Clock input (SCK). The output register is loaded with the contents of the shift register on the positive going transition of the Register Clock input (RCK). Since the RCK and SCK signals are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3-state, the VHC595 can be directly connected to an 8-bit bus. This register can be used in serial- -parallel conversion, data receivers, etc. -toThe internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
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16 9
SOIC-16 D SUFFIX CASE 751B
VHC595 AWLYYWW
1 8
16
9
TSSOP-16 DT SUFFIX CASE 948F
VHC 595 AWLYWW
1
8
16
9
* * * * * * * * * * *
High Speed: fmax = 185MHz (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 1.0V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V
These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
SOIC EIAJ-16 M SUFFIX CASE 966 A WL YY WW A WL Y WW
VHC595 ALYW
1 8
= Assembly Location = Wafer Lot = Year = Work Week A L Y W = Assembly Location = Wafer Lot = Year = Work Week
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC74VHC595D MC74VHC595DR2 MC74VHC595DT Package SOIC--16 SOIC--16 TSSOP--16 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail 2000 Units/Reel 2500 Units/Reel 50 Units/Rail 2000 Units/Reel
MC74VHC595DTEL TSSOP--16 MC74VHC595DTR2 TSSOP--16 MC74VHC595M MC74VHC595MEL SOIC EIAJ--16 SOIC EIAJ--16
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 4 -
1
Publication Order Number: MC74VHC595/D
MC74VHC595
PIN ASSIGNMENT
QB QC QD QE QF QG QH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA SI OE RCK SCK SCLR SQH
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MC74VHC595
LOGIC DIAGRAM
SERIAL DATA INPUT 14 15 1 2 3 SHIFT REGISTER STORAGE REGISTER 4 5 6 7 SCK SCLR RCK OE 11 10 12 13 9 SQH SERIAL DATA OUTPUT
SI
QA QB QC QD QE QF QG QH PARALLEL DATA OUTPUTS
IEC LOGIC SYMBOL
OE RSK SCLR SCK SI
13 12 10 11 14
EN3 C2 SRG8 R C/1 1D 2D 3 15 1 2 3 4 5 6 2D 3 7 9 QA QB QC QD QE QF QG QH SQH
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MC74VHC595
EXPANDED LOGIC DIAGRAM
OE 13
RCK
12
SI
14
D SRA R D SRB R D SRC R D SRD R D SRE R D SRF R D SRG R D
Q
D STRA
Q
15
QA
Q
D STRB
Q
1
QB
Q
D STRC
Q
2
QC
Q
D STRD
Q
3
QD PARALLEL DATA OUTPUTS
Q
D STRE
Q
4
QE
Q
D STRF
Q
5
QF
Q
D STRG
Q
6
QG
Q SRH
D STRH
Q
7
QH
SCK
11 R
SCLR
10
9
SQH
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MC74VHC595
FUNCTION TABLE
Inputs Reset (SCLR) L H H H Serial Input (SI) X D X X Shift Clock (SCK) X L, H, L, H, Reg Clock (RCK) L, H, L, H, X Output Enable (OE) L L L L Shift Register Contents L DSRA; SRNSRN+1 U U Resulting Function Storage Register Contents U U ** SRNSTRN Serial Output (SQH) L SRGSRH U * Parallel Outputs (QA - QH) U U ** SRN
Operation Clear shift register Shift data into shift register Registers remains unchanged Transfer shift register contents to storage register Storage register remains unchanged Enable parallel outputs Force outputs into high impedance state
X X X
X X X
X X X
L, H, X X
L L H = High--to--Low = Low--to--High
* * *
U ** **
* * *
U Enabled Z
SR = shift register contents D = data (L, H) logic level inputs STR = storage register contents U = remains unchanged
* = depends on Reset and Shift Clock ** = depends on Register Clock input
MAXIMUM RATINGS*
Symbol VCC Vin Vout IIK IOK Iout ICC PD Tstg DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package Parameter Value - 0.5 to + 7.0 - 0.5 to + 7.0 - 0.5 to VCC + 0.5 -- 20 20 25 50 500 450 - 65 to + 150 Unit V V V mA mA mA mA mW _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high--impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Vout TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time VCC = 3.3V 0.3V VCC =5.0V 0.5V Parameter Min 2.0 0 0 -- 55 0 0 Max 5.5 5.5 VCC + 125 100 20 Unit V V V _C ns/V
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MC74VHC595
The JA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below.
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 110 C TJ = 120 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 1. Failure Rate vs. Time Junction Temperature
DC ELECTRICAL CHARACTERISTICS
Symbol VIH Parameter Minimum High--Level Input Voltage Test Conditions VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 VIN = VIH or VIL IOH = -- 50 A VIN = VIH or VIL IOH = --4 mA IOH = --8 mA VOL Maximum Low--Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 50 A VIN = VIH or VIL IOL = 4 mA IOL = 8 mA IIN ICC IOZ Maximum Input Leakage Current Maximum Quiescent Supply Current Three--State Output Off--State Current VIN = 5.5 V or GND VIN = VCC or GND VIN = VIH or VIL VOUT = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 0 to 5.5 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4.0 0.25 2.0 3.0 4.5 TA = 25C Min 1.5 2.1 3.15 3.85 0.59 0.9 1.35 1.65 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 40.0 2.5 Typ Max TA = 85C Min 1.5 2.1 3.15 3.85 0.59 0.9 1.35 1.65 1.9 2.9 4.4 2.34 3.66 0.1 0.1 0.1 0.52 0.52 1.0 40.0 2.5 A A A V Max TA = 125C Min 1.5 2.1 3.15 3.85 0.59 0.9 1.35 1.65 Max Unit V
VIL
Maximum Low--Level Input Voltage
V
VOH
Minimum High--Level Output Voltage VIN = VIH or VIL
V
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MC74VHC595
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) Propagation Delay, SCK to SQH Test Conditions VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V VCC = 5.0 0.5 V tPHL Propagation Delay, CPLR to SQH VCC = 3.3 0.3 V VCC = 5.0 0.5 V tPLH, tPHL Propagation Delay, RCK to QA--QH VCC = 3.3 0.3 V VCC = 5.0 0.5 V tPZL, tPZH Output Enable Time, OE to QA--QH VCC = 3.3 0.3 V RL = 1 k VCC = 5.0 0.5 V RL = 1 k tPLZ, tPHZ Output Disable Time, OE to QA--QH VCC = 3.3 0.3 V RL = 1 k VCC = 5.0 0.5 V RL = 1 k CIN COUT Input Capacitance Three--State Output Capacitance (Output in High--Impedance State), QA--QH CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF Min 80 135 Typ 150 185 8.8 11.3 6.2 7.7 8.4 10.9 5.9 7.4 7.7 10.2 5.4 6.9 7.5 9.0 4.8 8.3 12.1 7.6 4 6 13.0 16.5 8.2 10.2 12.8 16.3 8.0 10.0 11.9 15.4 7..4 9.4 11.5 15.0 8.6 10.6 15.7 10.3 10 Max TA = 85C Min 70 115 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 15.0 18.5 9.4 11.4 13.7 17.2 9.1 11.1 13.5 17.0 8.5 10.5 13.5 17.0 10.0 12.0 16.2 11.0 10 10 Max TA = 125C Min 70 115 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 15.0 18.5 9.4 11.4 13.7 17.2 9.1 11.1 13.5 17.0 8.5 10.5 13.5 17.0 10.0 12.0 16.2 11.0 10 10 pF pF ns ns ns ns ns Max Unit MHz
tPLH, tPHL
Typical @ 25C, VCC = 5.0V 87 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no--load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.8 -- 0.8 Max 1.0 -- 1.0 3.5 1.5 Unit V V V V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
VCC V 3.3 5.0 3.3 5.0 TA = 25_C Typ Limit 3.5 3.0 8.0 5.0 TA = - 40 to 85C Limit 3.5 3.0 8.5 5.0 TA = - 55 to 125C Limit 3.5 3.0 8.5 5.0 Unit ns ns
Symbol tsu tsu(H)
Parameter Setup Time, SI to SCK Setup Time, SCK to RCK
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MC74VHC595
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol tsu(L) th th(L) trec tw tw(L) Parameter Setup Time, SCLR to RCK Hold Time, SI to SCK Hold Time, SCLR to RCK Recovery Time, SCLR to SCK Pulse Width, SCK or RCK Pulse Width, SCLR VCC V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Typ
Limit 8.0 5.0 1.5 2.0 0 0 3.0 2.5 5.0 5.0 5.0 5.0
Limit 9.0 5.0 1.5 2.0 0 0 3.0 2.5 5.0 5.0 5.0 5.0
Limit 9.0 5.0 1.5 2.0 1.0 1.0 3.0 2.5 5.0 5.0 5.0 5.0
Unit ns ns ns ns ns ns
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MC74VHC595
SWITCHING WAVEFORMS
tw SCK 50% tw 1/fmax tPLH SQH 50% VCC tPHL VCC GND SCLR tPHL SQH 50% VCC trec SCK 50% 50%
VCC GND
VCC GND
Figure 2.
Figure 3.
RCK
50%
VCC GND tPLH tPHL
OE
50% tPZL tPLZ
VCC GND HIGH IMPEDANCE VOL +0.3V VOH --0.3V HIGH IMPEDANCE
QA--QH QA--QH
50% VCC tPZH tPHZ
QA--QH
50% VCC
50% VCC
Figure 4.
VCC VALID SI 50% tsu SCK or RCK th 50% GND VCC GND VCC GND RCK SCK
Figure 5.
SCLR
50%
50% tsu(H) 50% tw
VCC GND VCC GND
Figure 6.
Figure 7.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 8.
Figure 9.
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MC74VHC595
TIMING DIAGRAM
SCK SI SCLR RCK OE
QA QB QC QD QE QF QG QH SQH NOTE: output is in a high--impedance state.
INPUT EQUIVALENT CIRCUIT
INPUT
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MC74VHC595
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B--05 ISSUE J
-A 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
1
8
-B -
P 8 PL 0.25 (0.010)
M
B
M
G F
K C -T SEATING PLANE
R X 45
D 16 PL 0.25 (0.010)
M
M
J
T
B
S
A
S
TSSOP-16 DT SUFFIX CASE 948F--01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9
2X
L/2
J1 B --USECTION N-N J
L
PIN 1 IDENT. 1 8
N 0.15 (0.006) T U
S
0.25 (0.010) M
A --VN F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) - - SEATING -TPLANE
--W-
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
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MC74VHC595
PACKAGE DIMENSIONS
SOIC EIAJ-16 M SUFFIX CASE 966--01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z
D A VIEW P c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.78 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.031
e
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHC595/D

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